Hitherto, in processors such as central processing units (CPUs), a technology in which an instruction is extended by making an instruction length a variable length has been typically used. Processors have an execution queue having a plurality of entries for storing instruction information and the like used to execute an instruction, and an entry of an execution queue is assigned to each instruction.
When the number of instructions to be stored in an execution queue is to be increased, it is desired to connect circuits in series for selecting an instruction from a plurality of entries possessed by the execution queue. Then, it is desired to connect selection circuits that select an instruction from a plurality of entries of the execution queue at many execution pipeline stages. When selection circuits are connected at many stages in this manner, the selection by the selection circuits of many stages may not be completed within a period of one clock cycle of the operating frequency of the processor. That is, this causes the operating frequency of the entire processor to decrease. In other words, leads to a decrease in the processing performance of the processor.
In contrast, in a technique in which the above mentioned variable length instruction is used, the total size of instructions in the entire program increases, but the number of instructions in the entire program does not increase. That is, it is not necessary to increase the number of instructions that can be stored in the execution queue, and the number of entries in the execution queue does not increase. That is, the amount of information per instruction stored within the entry in the execution queue increases, but the number of entries to be selected does not increase. Therefore, although in the circuit that selects an instruction from the execution queue, an increase is made in the parallel direction (bit width direction) such as the width of bits to be selected, the number of steps to be carried out in the selection circuit that performs selection is not changed. Thus, no increase is made in the series direction (series of gate stages direction or series of pipeline stages direction). Therefore, a large influence is not exerted on the operating frequency of the processor. Furthermore, in the above described technique of using a variable instruction length, after an instruction decoder decodes an instruction opcode, since the instruction opcode is not used, it is not necessary to store the instruction opcode itself.
[Patent Document 1] Japanese laid-open Patent Publication No. 2000-284962
[Patent Document 2] Japanese laid-open Patent Publication No. 2006-92158
[Patent Document 3] Japanese laid-open Patent Publication No. 2001-296999